The field of the present invention relates generally to semiconductor wafer characterization and more specifically to using scatter parameter contour mapping for transistor wafer characterization.
A chief determinant of a profitable semiconductor manufacturing operation is the maintenance of a high production yield. The worldwide semiconductor market is growing at a double-digit clip and is forecast to reach $250 billion by the year 2003. The factors driving the growth in the semiconductor manufacturing industry include such trends as the digital home, the global communications explosion, personal mobility and e-commerce. Improving manufacturing productivity remains a key factor in sustaining growth in the industry.
The semiconductor sector has typically tolerated a much lower and a much broader range of production yields running between 20 percent and 80 percent. These figures, while strikingly low by the standards of other manufacturing sectors, are often justified by citing the challenges and circumstances unique to the semiconductor manufacturing environment. The exacting requirements of clean rooms together with the large number of processes required to develop submicron components increase the likelihood of mistakes and failure in the process. Also, defective parts cannot be unbolted, replaced, or re-machined as is possible in other manufacturing sectors such as automotive production.
Device fabrication is commonly thought to take place in a series of four stages (depicted in FIG. 1) as adapted from Van Zant, Peter, Microchip Fabrication, A Practical Guide to Semiconductor Processing, Fourth Edition, McGraw Hill, 2000, p. 85. Stage 1 is the preparation stage where a crystalline silicon ingot is grown and purified from sand. It is here that individual wafers are prepared and xe2x80x9cslicedxe2x80x9d from the ingot. Stage 2 is the fabrication, or device fabrication stage. Layering, patterning, doping, and heat treatment are among the technologies employed during this stage to create the chips, called die, that become the electronic components in the final packaged product. In the fabrication stage, stage 3, precision electrical testing of individual die is performed. Usually only a representative sample of the total number of die on the wafer is selected from the wafer for testing. This stage is sometimes called the wafer sort stage because bad die are sorted from good die based on the results of the electrical tests. Many different measurements may be taken during the test phase using sophisticated manufacturing test equipment, or simple manual techniques. Though the tests employed are electrical in nature, they are crucial in pinpointing problems in process quality. In the final packaging stage, stage 4, the die are packaged before being placed into production as live electronic components. Packaging takes many forms but in every case the package chosen helps to protect the product from the harsh operating environment in which the product will operate.
Of chief concern to the manufacturing engineer is a quantity known as total production yield. Total production yield is particularly vulnerable to the wafer sort stage of the fabrication process. FIG. 2 summarizes the major considerations that concern manufacturing yield as adapted from Van Zant, Peter, Microchip Fabrication, A Practical Guide to Semiconductor Processing, Fourth Edition, McGraw Hill, 2000. Total production yield is defined to be the product of three yield measures taken at three yield measurement points: wafer fabrication, wafer sort, and packaging. Mathematics restricts the total production yield to a value no higher than the lowest of these three yield values. Industry statistics show that the wafer sort yield is historically the lowest of the three yields. Thus, from the standpoint of process improvement, efforts to boost the wafer sort yield have a direct impact on improving the overall production yield.
By way of example, FIG. 3 represents a flow diagram of a known laterally-diffused metal oxide semiconductor (xe2x80x9cLDMOSxe2x80x9d) power transistor wafer sort process. The LDMOS wafer begins its journey through the wafer sort process after first completing a front-end fabrication process. Step 305 represents the beginning of the wafer sort. Wafers are completely diced, and die lot numbers are assigned to wafers to track the origin of each individual die. In step 310, the die samples are chosen, ensuring that at least one die sample is taken from each quadrant of the wafer. This helps to guarantee a uniform characterization of die across the wafer surface. However, a total sample size of only four devices per wafer is not uncommon. In step 315, each sample die is fully packaged as a functional product prior to testing. Packaging is necessary largely to provide heat dissipation because the high power, large signal probes placed on the wafer during testing cause the wafer to radiate a lot of heat.
The heart of the product test is the DC and RF test cycle that begins with step 345. The battery of tests performed seeks to characterize the electrical behavior of the transistor device. The tests come in one of two broad categories. In one instance, the device undergoes DC testing in order to characterize the direct current behavior of the device. In the second category of test, the devices are placed under a RF probe in order to characterize the product""s response to large signal radio frequency (RF) input. In step 320, if the device under test fails to pass any one of the DC tests or RF tests, the entire die lot from which the device was removed will be discarded (step 325). Only if all sample die from a single wafer pass both the DC test and the RF test will the wafer be delivered to the back-end process (step 340) for final product assembly. RF tests require the extraction and packaging of a die sample prior to testing. RF testing is also partly responsible for the low wafer sort yield that is accepted in the microchip fabrication industry today. Under the current testing methodology, if a device under test fails to meet predetermined performance specifications, the entire wafer from which that device was extracted is scrapped
The current methodology is undesirable for a number of reasons. For one, the fate of each die on the wafer turns on the success or failure of a test performed on a very small subset of the devices on the wafer. Plenty of untested, but good die are consequently discarded, making the wafer sort stage a very wasteful process. Furthermore, the current testing methodology, which requires that the device under test be extracted from the wafer and packaged prior to testing, fails to isolate the parasitic effects of the package and other components from the effects of the tests on the device itself. This leads to innaccurate test results in many cases.
Thus, improvements in semiconductor wafer testing processes are desirable, especially those that increase wafer sort yield, while maintaining or improving the accuracy of the transistor device characterization process.
The present invention is directed to a system, and methods of its use, for characterizing semiconductor device wafers, such as LDMOS wafers in a preferred embodiment, by measuring small signal scatter parameter measurements of a representative sample of die to create a contour map of a wafer surface. Those die which fail to meet performance specifications are marked as bad die before the wafer is sent to a back-end process, where the unmarked good die are extracted and assembled into working products. By using enhanced S parameter mapping for characterizing the die, only those die marked as bad die need be discarded. Thus, instead of scrapping an entire wafer die lot based on the failure of a single die from that wafer, the wafer sort yield may be dramatically increased. The increase in wafer sort yield in turn, increases total production yield.
Other and further aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.